Evaluating the Applicability of LLM Inference Optimizations on Apple Silicon

cs.LG cs.DC Kyrylo Yemets, Andrii Yaroshevych, Victor Muryn, Ostap Khomenko, Pavlo Kryven, Maksym Kmet, Maksym Shamrai, Mariya Hirna · Oct 22, 2026
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What it does
Apple Silicon dominates local LLM inference, yet nearly every published optimization is designed and benchmarked on NVIDIA server GPUs under batched serving workloads. This paper asks which speedups survive when moved to single-request,...
Why it matters
This paper asks which speedups survive when moved to single-request, unified-memory Apple machines, evaluating four families—KV-cache pruning, speculative decoding, ported CUDA kernels, and post-training quantization—across four Apple...
Main concern
The paper delivers a timely, well-controlled empirical assessment that overturns the implicit assumption that CUDA-validated optimizations will naturally help Apple Silicon. The four-family sweep, explicit taxonomy for kernel porting...
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Plain-language introduction

Apple Silicon dominates local LLM inference, yet nearly every published optimization is designed and benchmarked on NVIDIA server GPUs under batched serving workloads. This paper asks which speedups survive when moved to single-request, unified-memory Apple machines, evaluating four families—KV-cache pruning, speculative decoding, ported CUDA kernels, and post-training quantization—across four Apple devices with matched RTX 4090 controls. The central finding is that a reported speedup is not an intrinsic property of a technique but a joint function of technique, runtime, hardware contract, and workload regime.

Critical review
Verdict
Bottom line

The paper delivers a timely, well-controlled empirical assessment that overturns the implicit assumption that CUDA-validated optimizations will naturally help Apple Silicon. The four-family sweep, explicit taxonomy for kernel porting (TRANSFERS, HW-GAP, RUNTIME, N/A), and honest reporting of negative results make the argument credible. The evidence supports the overarching claim that portability depends on the interaction of bottleneck, workload, and runtime; however, the absence of quality evaluation for pruning and the extremely narrow megakernel scope limit the strength of some specific conclusions.

“Apple Silicon is among the most widely used platforms for local LLM inference, yet nearly all inference optimizations are designed and validated on server-class NVIDIA GPUs under batched serving workloads. Which optimizations retain their benefits when moved to Apple Silicon, and what determines their applicability?”
paper · Abstract
“The unifying result is that a reported speedup is not a portable property of a technique alone, but a joint function of technique, runtime, hardware contract, and workload regime.”
paper · Section 3
What holds up

The experimental design is a genuine strength. Apple devices spanning three GPU generations are compared against a matched RTX 4090 under aligned batch-one workloads, and the authors reject easy generalizations. The speculative-decoding analysis is particularly careful: every method is shown to lose end-to-end throughput in the principal benchmark, yet the authors also identify configuration-specific positive cases and explain why decode-side acceptance does not imply E2E gains. The Metal kernel taxonomy (TRANSFERS, HW-GAP, RUNTIME, N/A) transforms opaque porting intuition into actionable decision criteria. Quantization results are equally nuanced, showing that the best runtime and format depend on the specific chip rather than simply on bit-width.

“No configuration in this matched comparison improves E2E throughput.”
paper · Section 2.2.1
“A mechanism that fails to port does so for one of four reasons. Conflating them is what makes porting work feel arbitrary; separating them makes the outcome predictable.”
paper · Section 2.3.1
Main concerns

Two limitations stand out. First, KV-cache pruning is evaluated without measuring downstream output quality; the authors explicitly exclude this as outside scope, which means the latency gains for SnapKV and ExpectedAttention come with an unquantified accuracy cost that is material to real deployment. Second, the megakernel case study is billed as exploratory, but its scope is so narrow—one LFM2.5-8B-A1B MoE block on one M4 Pro—that its broader interpretive weight should be treated cautiously. A third concern is that some cross-platform speculative-decoding comparisons are confounded by runtime differences (MLX vs PyTorch/vLLM) rather than isolating hardware; the authors acknowledge this, but it weakens the hardware-only attribution. Finally, FastKVzip is reported to slow execution on both platforms without a satisfying causal explanation beyond overhead dominance.

“Evaluating pruning-induced changes in output quality is outside our scope; these effects are expected to be comparable across platforms using identical pruning algorithms and configurations.”
paper · Section 2.1.1
“We treat the following experiment as an exploratory case study, not as one of the primary porting results. It covers one LFM2.5-8B-A1B MoE block on one M4 Pro under MLX, and the implementation was not evaluated broadly enough to support a claim about every model, Apple GPU or possible megakernel design.”
paper · Section 2.3.5
Evidence and comparison

The evidence largely supports the claims. The paper is commendably fair to prior work: it notes that reported 2–6× speculative-decoding gains on server GPUs arise under different models, workloads, and runtimes, and it does not overstate hardware causation where runtime confounds exist. The Marlin characterization—that it targets batched serving on NVIDIA GPUs—is consistent with the original paper, which indeed emphasizes batchsizes up to 16–32. The FlashInfer and MoE porting analyses are backed by kernel-level and end-to-end measurements, and the split-KV reversal on older Apple GPUs is traced to a quantifiable dispatch-and-partials overhead. One weakness is that the positive cases for speculative decoding (Table 2) are drawn from supplementary, uncontrolled configurations, so they serve as existence proofs rather than a ranked ranking of methods.

“Speculative decoding can accelerate particular Apple Silicon configurations, but the published server-GPU gains do not transfer robustly to the principal local chat benchmark.”
paper · Section 2.2.3
“This paper resolves this question positively by describing the design of Mixed-precision Auto-Regressive LINear kernels, called MARLIN. Concretely, given a model whose weights are compressed via quantization to, e.g., 4 bits per element, MARLIN shows that batchsizes up to 16-32 can be supported with close to maximum ($4\times$) quantization speedup”
Reproducibility

The paper provides unusually detailed experimental metadata, including exact model checkpoints, quantization group sizes, draft budgets, prompt distributions, and warm-up protocols in Appendix A.1. Metal kernel source appears inline in listings, which helps readers reconstruct the ports. However, there is no explicit statement that the full benchmark harness or ported kernels will be released as open-source, and several comparisons are withheld because of implementation mismatches rather than reported. Hyperparameters for pruning methods (compression ratios, context lengths) are clearly tabulated, and the split-KV routing uses a measured per-architecture table rather than opaque heuristics. Reproducing the end-to-end numbers should be feasible for readers with access to the same MLX versions and hardware, though the lack of version-pinned software artifacts raises a barrier.

“The principal comparison uses MLX with batch size one and concurrency one on M2 Pro and M3 Ultra. Targets are mlx-community/Qwen3-4B-4bit and BF16 Qwen/Qwen3-4B. The 100-prompt conversational dataset contains 46 tool-calling and 54 regular-chat samples, with a mean prefill length of 1,776 tokens.”
paper · Appendix A.1
“Two comparisons were attempted and are withheld rather than reported. Marlin itself... The MoE gather... A fused-MoE comparison is future work; the N/A verdict of §2.3.4 rests on the Apple-side prefill result instead.”
paper · Section 2.3.6
Abstract

Apple Silicon is among the most widely used platforms for local LLM inference, yet nearly all inference optimizations are designed and validated on server-class NVIDIA GPUs under batched serving workloads. Which optimizations retain their benefits when moved to Apple Silicon, and what determines their applicability? We evaluate four optimization families: KV-cache pruning, speculative decoding, ported GPU kernels, and post-training quantization. Experiments span four Apple machines under a common single-request decode workload, with matched RTX 4090 comparisons where possible. KV-cache pruning can reach up to 1.75 times end-to-end throughput on Apple but can reduce throughput on desktop NVIDIA GPUs. Under the common benchmark, all evaluated speculative decoding methods reduce throughput on Apple, despite reported 2-6 times gains on server GPUs. CUDA kernel designs transfer only partially: public Metal lacks asynchronous copy, and batch-one decode makes several serving-oriented mechanisms inapplicable, although transferable components yield up to 1.20 times decode throughput. Quantization gains vary by machine. Across four families, a reported speedup is not a portable property of a technique alone but a joint function of technique, runtime, hardware contract, and workload regime.

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