NN-Based Transistor Modeling for Ultra-Fast SPICE Simulation and Standard Cell Library Characterization
This paper proposes replacing the physics-based BSIM-CMG compact model with tiny MLPs (8–16 neurons) to predict drain current and charges for a 3 nm nanosheet, then embedding them in Verilog-A to perform a full standard cell library characterization and subsequent static timing analysis on industrial-scale circuits. The authors claim sub-percent delay and power errors alongside up to 8× faster library characterization, positioning the approach as a viable alternative to equation-based transistor models in modern EDA flows.
The paper presents a credible, end-to-end engineering demonstration that extremely small neural networks can survive the harsh demands of standard cell library characterization and timing signoff, but its boldest speedup claims rest on a Verilog-A baseline rather than the compiled C reference used in production. The NN16 model delivers stable, sub-0.2 % delay errors across 12 circuits and thousands of SPICE simulations, yet NN8 shows non-negligible error accumulation in internal power and capacitance, making the abstract headline figures somewhat selective.
The rigor of the evaluation pipeline is the paper’s main strength: unlike prior NN transistor modeling works that stop at individual IV curves or simple ring oscillators, the authors run 1,701 post-layout SPICE netlists across 71 combinational and sequential cells, then propagate the resulting libraries into STA for circuits up to 104,286 gates. The NN16 model achieves remarkably low average relative errors of 0.06 % for cell delay and 0.33 % for cell power during characterization, and the analog-level divider simulation shows visually indistinguishable waveforms against the BSIM-CMG reference.
The most significant limitation is that the speedup baseline is an interpreted Verilog-A BSIM-CMG model, which is acknowledged to be far slower than a compiled C implementation; therefore, the headline 8×–43× speedups may not translate to industrial flows using production-compiled models. Additionally, the smaller NN8 model exhibits visible capacitance inaccuracies near 0.4 V and blows up internal-power errors to as high as 4.8 %, yet the abstract highlights sub-0.11 % delay and 0.76 % total-power metrics that primarily reflect the larger NN16. The authors also rely on a Low-Precision Simulation (LPS) setup to reach the highest speedups, but this introduces accumulating delay deviations and makes some cells entirely unsuitable for characterization.
The evidence convincingly supports the narrower claim that a sufficiently large MLP can mimic a BSIM-CMG reference in a Verilog-A-to-Verilog-A shootout, but it does not demonstrate fidelity to physical silicon or to a production-compiled compact model. Comparisons to related work are generally fair the authors accurately note that prior NN-based models were tested only on limited circuits and rarely included pMOS but the "first time" framing for library characterization is an incremental advance over their own prior SPICE-integration work rather than a leap from isolated device modeling.
Reproducibility is impaired by the lack of released code, trained model weights, or the generated Verilog-A implementations. While the paper reports training details PyTorch, Adam with an initial learning rate of 0.001, iterative loss scheduling, and conversion functions for $I_D$ and $Q$ the exact coefficients, weight initialization, and Verilog-A unrolling are not provided. The GT3 open-source PDK is used for device data, but without the authors artifacts, independently replicating the 1,701-netlist characterization campaign and 12-circuit STA flow would be arduous.
Neural network (NN)-based transistor models have proven to be a promising solution to accelerate device modeling. Although these models demonstrated remarkable speedup in circuit simulations, they were not rigorously tested in complex tasks within standard EDA tool flows for chip design, which require very high transistor model precision to provide accurate results and converge properly. To investigate their full potential and promise, we develop NN-based transistor models that accurately predict the drain current and various charges for a 3nm nanosheet, and employ the models for a standard cell library characterization. This enables us to evaluate the accuracy and speedup under a very wide range of SPICE simulations, benchmarking our models against an industry-standard implementation. Since standard cell library characterization involves thousands of SPICE simulations, it serves as a great benchmark for transistor model quality and consistency. To further evaluate model accuracy, we also perform analog- and digital-level simulations for various complex circuits. Our experiments reveal that NN-based models are a valid alternative to existing transistor compact models, capable of producing accurate delay and power estimates with a much higher speed and convergence time compared to the conventional Verilog-A-based industry-standard (BSIM-CMG) transistor compact model. Our NNs achieve sub-0.11% and 0.76% errors for delay and total power evaluation on a wide range of circuits, while taking up to 8 times less time during the standard cell library characterization. Additionally, we provide comprehensive information and guidance on NN accuracy, unveiling the relationship between NN size and its effect on circuit simulation precision.
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