CktHGVAE: A Symmetric Design/State Heterogeneous Graph Variational Autoencoder for Transistor-level Analog/Mixed-signal Circuit Design and Analysis
CktHGVAE tackles analog/mixed-signal CMOS circuit automation by learning a joint latent manifold of design parameters and transistor-level operating states. The core idea is a symmetric heterogeneous graph VAE that treats SPICE-derived state variables and design variables equally as inputs and outputs, enabling closed-loop design verification without a separate surrogate model. This is significant because prior graph learning approaches for analog circuits largely rely on macromodel abstractions or topology generation, leaving fine-grained operating-state modeling underexplored.
The paper proposes a clean and practically promising idea—a vanilla heterogeneous GVAE with symmetric design/state variables and GraphSAGE message passing, verified in closed-loop against Ngspice. However, the evaluation is restricted to tiny DC operating-point datasets (≈1,000–2,000 samples), zero-shot transfer collapses outright in one scenario, and optimization is demonstrated on only one simple common-source amplifier with loose constraints. Whether the model scales to larger circuits, AC/transient analysis, or aggressive specifications remains entirely open.
The strongest elements are the rigorous closed-loop fidelity protocol and the elegant symmetric formulation. Every reported design candidate is checked against open-source SPICE simulation with the SkyWater 130nm PDK, yielding median $R^2$ values above 0.9 for single-ended amplifiers and an inverter using a single hyperparameter configuration without topology-specific tuning. This directly supports the claim that the latent space captures a physically meaningful manifold.
The model cannot function as a direct feed-forward surrogate: conditioning on a fixed set of design variables requires latent-space search with equality constraints rather than a single decoder pass.
Zero-shot cross-topology transfer is brittle and depends heavily on pretraining topology choice; Scenario A fails almost completely with a median $R^2$ near 0.007 for the held-out PMOS source-degenerated amplifier. Differential-pair circuits also require roughly twice the data to reach acceptable fidelity and still suffer from low in-domain sampling rates—as low as 36.3% for the 5-transistor OTA—indicating that the latent manifold is poorly covered for more complex circuits.
The quantitative evidence supports the narrow claim of DC operating-point reconstruction, but the latent-space optimization demonstration is limited to one topology (T1) with five lightly constrained targets, so robustness under aggressive specs is unproven. The qualitative comparison to prior work is accurate: the authors correctly distinguish their transistor-level state-variable approach from macromodel-based methods such as CktGNN, CktGen, and OPAMP-Generator. However, there is no quantitative head-to-head comparison, so readers cannot judge whether symmetric state modeling outperforms a macromodel-plus-separate-surrogate pipeline.
Reproducibility is mixed. The authors disclose the open-source PDK (SkyWater 130nm), simulator (Ngspice), dataset generation protocol, hyperparameters in Appendix A, and software versions. Yet no code repository or dataset link is provided, which blocks independent reproduction. The small sample sizes (≈1,000 circuits per topology) and training on a laptop also raise questions about whether the reported hyperparameters will transfer to larger, industrial-scale circuits.
We propose CktHGVAE, a heterogeneous graph variational autoencoder for transistor-level analog/mixedsignal CMOS circuits that takes not only design variables but also state variables as its inputs and outputs. With a single hyperparameter configuration without topology-specific tuning, comparison between model-generated and SPICE-simulated circuit operational states gives median R2 values above 0.9 for typical single-ended voltage amplifiers and the CMOS inverter, and 0.81-0.96 for differential amplifiers with larger datasets. Latent-space optimization in the PCA-reduced latent space with Bayesian optimization, evolutionary search, random search, and quasi-exhaustive search is demonstrated for a common-source voltage amplifier with NMOS input and resistive load, where the objective function is defined as a penalty for deviation from required circuit specifications. For each search strategy, 93.3 - 100% of all design candidates suggested by the model satisfy the required circuit specifications at the decoder output, and SPICE simulations verify that 90 - 100% of them indeed satisfy the requirements. The model pretrained on a batch of topologies can be transferred to unseen topologies without retraining at all, with zero-shot reconstruction median R2 values of 0.72-0.90 in three of four scenarios, including transfer from single-ended to differential topologies, although the transfer fidelity depends on the choice of pretraining topologies. Our demonstrations suggest that the proposed model can potentially serve as a basis for AMS CMOS circuit design automation.
Pick a starting point or write your own. Challenges run in the background, so you can keep reading while the AI investigates.
No challenges yet. Disagree with the review? Ask the AI to revisit a specific claim.