Overcoming Kernel Redundancy for Scaling Logic Gate Networks
Logic gate networks replace arithmetic operations with purely Boolean functions for highly efficient inference, yet scaling their width naively causes kernel redundancy and performance saturation. This work identifies that redundancy is most severe at the first gate level and proposes Dynamic Logic Kernel (DLK) and Early-stage Dynamic Logic Kernel (EDLK), which use input-dependent Boolean routing to specialize kernel groups or first-level gate groups. The result is improved kernel diversity and better accuracy-efficiency trade-offs under width scaling, advancing the practicality of discrete logic-based deep learning.
Overall, the paper makes a solid contribution to an underexplored problem: how to scale width in differentiable logic gate networks without inducing redundant kernels. The authors introduce a custom function-aware tree-edit-distance metric and use it to show that naive width scaling reduces kernel diversity (Table 1), then propose DLK and EDLK to address this via purely Boolean routing. The ablation comparing learned versus frozen random routing (Table 3) strongly supports the claim that learned input-dependent selection matters. However, the evaluation is limited to relatively small image classification benchmarks, and the paper itself acknowledges that "extending the gate-based formulation to substantially larger-scale architectures, such as LLM-scale models, remains challenging" (Section 6).
The diversity analysis is the paper's strongest element. The proposed function-aware tree edit distance metric (Eq. 3) captures meaningful functional differences between Boolean gates—for example, $\delta_f(\oplus,\vee)=1$ versus $\delta_f(\oplus,\wedge)=3$—and the level-wise decomposition (Figure 4) provides clear empirical justification for EDLK's early-stage design. The routing ablation is also persuasive: "frozen random routing provides only marginal improvements over the static baseline, whereas learned routing yields substantially larger gains on both datasets" (Section 5.2, Table 3).
The evaluation scope is narrow. The authors test only on image classification datasets up to Tiny-ImageNet, and explicitly note that "our evaluation mainly focuses on image classification, leaving dense prediction tasks such as image restoration, semantic segmentation, and optical flow unexplored" (Section 6).
A second issue is that depth scaling remains unresolved: Figure 7 shows that "increasing the depth does not yield additional performance gains; instead, accuracy gradually saturates or slightly decreases for all methods," suggesting the proposed mechanisms do not address deeper optimization or discretization gaps. Finally, key hyperparameters such as the balancing loss weight $\lambda_{bal}$ and the temperature $\tau$ in softmax routing (Eq. 8) are stated but not ablated, leaving sensitivity unclear.
The evidence supports the central claim. Table 1 shows that "For the conventional method, diversity remains low and further decreases as width increases, indicating that additional kernels become increasingly redundant," while DLK maintains high diversity. This correlates with accuracy trends in Figure 1 and Figure 5. Comparisons to the static Logic Kernel and IWP baselines are fair under matched width, and the hardware synthesis results (Table 6) are a genuine plus: "EDLK achieves higher accuracy while requiring lower latency, energy, and area" than a wider static baseline. That said, the cross-model comparison in Table 7 is only on MNIST, a dataset where conclusions about efficiency may not transfer to harder tasks.
The paper gives substantial architectural and training detail in Appendix A, including stage width multipliers, logic tree depth $d=3$, and thermometer encoding bits. For optimization, the authors report: "Unless otherwise stated, the reported experiments are trained with AdamW for 200,000 iterations. The default batch size is 64 with an initial learning rate of 0.02" (Appendix A.2.2). However, no public code repository is mentioned, the thermometer threshold counts vary by dataset without justification beyond citation to prior work, and the router bit-width is "selected from $[15,31]$ according to the number of candidate groups $G$" without a precise mapping. These omissions would block exact reproduction.
Differentiable logic gate networks, which operate using only logic gates, have recently attracted attention as an efficient alternative to conventional neural networks. However, despite their efficiency, the scaling behavior of logic gate networks remains underexplored. By contrast, scaling model capacity is a central design principle in deep neural networks and typically leads to improved performance. This discrepancy raises a key question: Can similar scaling benefits also be achieved in logic gate networks? In this work, we focus on width as a primary scaling axis and conduct a systematic analysis of its behavior in logic gate networks. We observe that naive width scaling often introduces redundancy among logic kernels, limiting the effective use of additional kernels and leading to performance saturation. To address this limitation, we propose a dynamic logic kernel framework that reorganizes kernel utilization by promoting specialization across kernel groups. This enables the network to better utilize increased width via input-dependent kernel routing, while ensuring that both routing and computation are implemented entirely with gate-level Boolean operations at inference time. We further find that kernel redundancy is most pronounced at the first gate level, motivating an early-stage dynamic logic kernel strategy that concentrates adaptation at this level. Experimental results demonstrate that our approach improves kernel utilization and increases kernel diversity, leading to higher accuracy with improved parameter efficiency.
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